1. Field Of The Invention
The invention relates to control in a computer system and, more particularly, to a distributed pipeline microsequencer structure and method for controlling the computer.
2. Background Of The Invention
Pipelining an execution data path is one of several techniques to improve overall performance of a computer system. This results in a reduction of the amount of functionality that is required at any given stage in the computer, thus allowing higher clock speeds and therefore higher performance. A problem in pipelining is the latency that occurs when the pipeline flow is broken. The deeper the pipe, the greater the latency. Much effort is placed in assuring that pipeline breaks are minimized by proper structuring of microcode, but this technique is not always effective.
In a microcoded execution unit, the various functional structures, such as adders and data rotators, are controlled by specific control fields within the microcode word. A microcode word is used for controlling a single step of a complex computation algorithm such as an arithmetic divide. A complex algorithm may consist of many microcode words that are executed in some specific order to accomplish the algorithm. The execution of this algorithm requires both the serial execution of groups of microcode words and, in many cases, a choice of an alternate sequence as a function of some dynamic condition of the data. This change in sequencing creates the pipeline breaks and resultant latency delays.
An individual microcode word contains information in predefined fields that will cause certain operations to occur in the data path structures of the computer at the specific machine cycle time that the microcode word is executed. To specify the next microcode word to be executed, a defined field within a microcode word will contain the address of the location in the control store that contains the next sequential microcode word. As each microcode word is executed, its corresponding next address field provides the address within the control store that contains the next sequential microcode word to be executed. This field will automatically be utilized to access and provide the next microcode word for the next machine cycle.
A complex instruction-set microcoded computer executes the high level operators by executing a sequence of microcode words. This process is normally initiated by a code evaluation unit within the computer examining and providing an initial address of the microcode word sequence to the first stage of the microsequencer. At the termination of a microcode sequence, a mechanism is required to allow a request to be made for the initial address associated with the microcode word sequence of the next-to-be-executed high level operator.
The execution of an algorithm designed to execute a high level computer instruction utilizes both the sequential execution of microcode words and conditional execution of alternate sequences of microcode words as a function of dynamic data conditions. The penalty for aborting a pipeline can be quite severe and negate much of the performance improvement achieved by the pipeline.